High Frequency Limitations of Diode Frequency Multipliers'

A computer program has been written to investigate the design tradeoffs of high frequency diode frequency multipliers. Velocity saturation and breakdown have been included in a device model that is part of a nonlinear multiple reflection simulation. The device doping, epitaxial layer length and velocity vs. electric field curve are input parameters. The program has a search routine to match the diode input impedance and to optimize the load impedance to maximize the efficiency. The DC bias point choice varies the operation from a resistive to a reactive mode. A useful measure of the operating point is the input Q. Lower Q's correspond to more resistive operation and higher Q's correspond to varactor operation. The input Q also determines the ease of matching and the resulting sensitivity of the circuit design to small changes. This computer program has been used to investigate diode multiplier operation over an input frequency range from 100 to 300 GHz. The results give useful insight into diode multipliers. The optimum multiplier design for power is shown to be different than the optimum efficiency design. The best results at lower frequencies are varactor designs. The designs become more resistive with increasing frequency. The paper will give design details and a physical description of the tradeoffs. Introduction Diode based frequency multipliers are critical components in millimeter and submillimeter wave systems. These multipliers are the only convenient source of local oscillator power for frequencies above 200 GHz. The design of multipliers at lower frequencies is well established. A variety of useful design tools have been developed based on harmonic balance or multiple reflection techthques[1, 2]. Commercial software packages are also available[3, 4]. These programs depend on a voltage dependent equivalent circuit to describe the nonlinear device. However, as the operating frequency and RF level increases, these simple equivalent circuit descriptions of the device do not correctly describe the device behavior and a more detailed description of the device is needed. Recently velocity saturation effects have been shown to be important in multiplier operation[5, 6, 7]. Additional effects including the choice of doping level and the resulting breakdown voltage also need to be considered. There are also tradeoffs in choosing a resistive vs. reactive mode of operation. Many frequency multiplier designs use a Schottky diode as a varactor, or nonlinear capacitor, since, at least in the limit of low series resistance, a varactor multiplier can have a high conversion efficiency. A nonlinear resistance multiplier is limited to an efficiency of 1/n2, where n is the harmonic number. However, the conditions required for the reactive multiplier can lead to a high Q circuit at the input side of the multiplier. High Q circuits can be difficult to fabricate at high frequencies, are sensitive to small changes to the structure, and can have high loss. The goal of this paper is to examine the design tradeoffs of high frequency diode multipliers when the effects of velocity saturation, doping, breakdown voltage and the mode of operation are included. A nonlinear multiple reflection code based on a computer simulation discussed by East et. al. [8] that includes velocity saturation effects and diode breakdown has been used. The solution is embedded in an optimization loop that matches the input port and searches the output impedance plane to maximize multiplier efficiency. The semiconductor diode area, epitaxial layer doping and length, carrier velocity vs. electric field and dc bias point are input variables. Since different frequencies and dopings will be compared, the device areas are chosen so that the zero bias reactance at the frequency under consideration This work was supported by the Center for Space Terahertz Technology under contract No. NAGW-1334 and NASA/JPL under contract 960426.